Corrected some errors.

Memory access is now independend from the host by separating data- and address busses.
That means, on memory access to David65's memory, the host computer sees a read access to $FFFF.

U10 and U11 are deselected then and the resistor networks pull-up the address lines to $FFFF.

This was necessary to avoid side effects of reading any addresses within the host system, e.g. resetting IRQ flags of VIA chips.

Here's the latest schematic.

You are very welcome to post any questions / suggestions...

I would like to order one too! Immediatly!

Not yet.

Should create one, but everything's still very early alpha stage...